PCI-SIG President and Board Member, Al Yanes In this video, PCI-SIG President and Board Member, Al Yanes, shares and overview of PCI Express 5.0 and 6.0 specifications. Continuing the trend we set with the PCIe 5.0 specification, the PCIe 6.0 specification is on a fast timeline,” said Al Yanes, PCI-SIG Chairman and President.
“Due to the continued commitment of our member companies, we are on pace to double the bandwidth yet again in a time frame that will meet industry demand for throughput.” At the recent PCI-SIG Developers Conference 2019, the organization announced that PCIe 6.0 technology will double the data rate to 64 GT/s while maintaining backwards compatibility with previous generations and delivering power efficiency and cost-effective performance.
The PCIe 6.0 specification is actively targeted for release in 2021. PCI Express technology has established itself as a pervasive I/O technology by sustaining bandwidth improvements for five generations over two decades,” Dennis Martin, an analyst at Principled Technologies, said.
“With the PCIe 6.0 specification, PCI-SIG aims to answer the demands of such hot markets as Artificial Intelligence, Machine Learning, networking, communication systems, storage, High-Performance Computing, and more.”
Delivers 64 GT/s raw bit rate and up to 256 GB/s via x16 configuration
Utilizes PAM-4 (Pulse Amplitude Modulation with 4 levels) encoding and leverages existing 56G PAM-4 in the industry
Includes low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
Maintains backwards compatibility with all previous generations of PCIe technology